1. Field of the Invention
The invention relates to a clock multiplication circuit for converting a reference clock signal as inputted into an output clock signal having a frequency that is a multiple of the frequency of the reference clock signal.
2. Description of the Related Art
As a clock multiplication circuit using a reference clock signal as inputted for converting the reference clock signal into an output clock signal having a frequency that is a multiple of the frequency of the reference clock signal, there is known a multiplication PLL circuit. As the multiplication PLL circuit, there is known a multiplication PLL circuit 100 comprising, for example, a phase comparator circuit 110, a charge pump 120, a low pass filter (also referred to hereinafter merely as LPF) 130, a voltage control oscillator circuit (also referred to hereinafter merely as VCO) 140, and a frequency divider 150 as shown in FIG. 1. With the multiplication PLL circuit 100, the phase comparator circuit 110 compares the phase of a frequency-divided signal SD of the frequency divider 150 with that of a reference clock signal SR, and causes the charge pump 120 to deliver current corresponding to an up-signal and a down-signal, respectively, representing results of phase comparison, the current being integrated by the LPF 130 to be delivered as a voltage output. By inputting the voltage output to the VCO 140, an output clock signal ST at a frequency corresponding to the voltage output is delivered. The frequency divider 150 divides the frequency of the output clock signal ST. Thus, there is delivered the output clock signal ST at a frequency that is a multiple M, which is the reciprocal of a frequency-dividing ratio (1/M), of the frequency of the reference clock signal SR. Further, accuracy of the frequency of the output clock signal ST can be maintained by executing the phase comparison for PLL control once in every cycle of the reference clock signal SR.
With the multiplication PLL circuit 100, however, the up-signal or the down-signal, having a pulse width corresponding to a phase difference between the frequency-divided signal SD and the reference clock signal SR, is delivered from the phase comparator circuit 110, and these signals are processed in an analog fashion, thereby controlling the frequency of the VCO 140. Accordingly, in order to adjust a loop gain and other circuit characteristics of the multiplication PLL circuit so as to be in a proper state, it has been necessary to adjust the characteristics of analog circuits such as the phase comparator circuit 110, charge pump 120, LPF 130, VCO 140, frequency divider 150, and so forth, which is inconvenient. Furthermore, there have been user requests for shortening lockup time.